This invention relates to a folding circuit for converting an analog signal into a folded signal, and to an analog-to-digital converter (ADC) which makes use of such a folding circuit.
High-resolution image processing and high-precision instrumentation systems require high-resolution, high-speed ADC's. For the case of an HDTV (high definition TV) ADC or of a B-ISDN ADC, a resolution of 10 bits is required in addition to a conversion speed of 75 MSPS. Instrumentation systems (for example, a digitizing oscilloscope) require ADC's capable of a resolution of 10 bits and of a conversion speed of over 100 MSPS. In the application of the HDTV or B-ISDN, low-power ADC's are very attractive. For example, when used in an HDTV transmission system, signals Y, Pb, and Pr each require an ADC. This presents a problem that power consumption by such ADC's forms a considerable percentage of all power consumed in the system. An ADC with less power consumption is required, accordingly. Meanwhile, ADC's, when applied to HDTV camera devices, cannot depend upon air-cooling by means of a fan which produces unwanted noises. Therefore, less power consumption must be achieved so that an ADC allows itself to cool down spontaneously, without depending upon any forced-air cooling means. Generally, ADC's of this type are sealed within a ceramic package. If, however, less power consumption (less heat generation) is accomplished, this allows use of much cheaper plastic packages. Therefore, a circuit technology capable of reducing the number of elements and achieving lower power consumption is now required.
The prior art discloses many different ADC's. For example, Japanese Patent Application, published under No. 3-274918, shows a parallel and a serial-parallel ADC. Japanese Patent Application, published under No. 62-175018, shows a sequential-comparison ADC. Among these ADC's, the parallel ADC is simple, conforms to the principle of analog-to-digital conversion, and operates at high speeds. The parallel ADC, however, requires a great number of elements and consumes much power.
Conventional high-speed ADC's have a master/slave latch configuration in order to drive an encoder. Since the encoder lines are heavily loaded and a greater amplitude of an output signal is required, it is preferable for an ADC to employ such a master/slave latch configuration so as to drive the encoder lines with digitized data over a clock cycle for a high-speed operation. FIG. 15 illustrates a conventional parallel ADC having a master/slave latch configuration, this ADC comprising (a) a reference resistor row 1 formed by reference resistors connected in series, (b) a pre-amplifier array 2 formed by pre-amplifiers PA1 to PA7, (c) a master-comparator latch array 3 formed by master-comparator latches MCL1 to MCL7 corresponding to the pre-amplifiers PA1 to PA7, (d) a slave latch array 4 formed by slave latches SL1 to SL7 corresponding to the master-comparator latches MCL1 to MCL7, (e) an analog input terminal 5 to which an analog input voltage Vin is applied, and (f) an exclusive-OR (XOR) gate latch array 6 formed by XOR gate latches XOR1 to XOR7. Each PA is supplied with Vin through one input thereof together with a reference voltage Vr, divided and generated by each resistor of the reference resistor row 1, through the other input. The outputs of MCL1 to MCL7 are received by SL1 to SL7 in a corresponding manner. Each XOR gate latch executes an XOR operation between outputs of two adjacent slave latches, thereby giving an output so as to drive an encoder via dotting transistors (not shown).
Each MCL which contains a differential amplifier (not shown) makes a comparison between Vin and Vr during the comparison mode, thereafter providing a positive feedback to the differential voltage produced during the comparison mode for latching.
A signal conversion circuit of FIG. 13 is disclosed in the "IEEE Transactions on Nuclear Science" (Vol, NS-22, Feb. 1975, pp 446-451), which makes use of a differential amplifier. This technique shows a circuit called a folding circuit in which the outputs of plural differential amplifiers are superimposed. Vin is applied to each differential amplifier through one input thereof while each Vr (Vr1&lt;Vr2&lt;Vr3) is applied through the other input. For the case of a folding waveform corresponding to the folding circuit of FIG. 13, the differential direction makes an inversion at Vr1, Vr2, and Vr3 with respect to Vin (see FIG. 14).